This invention relates generally to programmable logic array circuitry and more particularly, it relates to an improved logic circuit arrangement for performing synchronous dual word decoding utilizing a programmable logic array which is formed with a reduced number of transistor counts than has been traditionally available.
In recent years, there has arisen the need of incorporating various functionalities onto a single semiconductor integrated circuit chip, especially when designing large scale integrated (LSI) circuits or very large scale integrated (VLSI) circuits. Thus, different modules or blocks representing unique operations, either partially dependent or totally independent of one another, may now be formed on the same integrated circuit. The activation of these modules are determined by control commands which are received by these modules. Each of the blocks on the integrated circuit are typically assigned a distinct control command. As the number of modules becomes increasingly higher on the same integrated circuit, the corresponding number of required control commands will likewise become higher.
It is generally known that decoding of these control commands or operational codes (opcode words) can be achieved by a programmable logic array (hereinafter called PLA). Hence, with the increased number of control commands the size of the PLA that decodes the opcode words becomes larger and thus require larger amounts of chip space. Accordingly, when the programmable logic arrays are implemented on an integrated circuit it would be desirable to minimize the number of circuit components used in order to reduce manufacturing and assembling costs. Further, the larger the size of the PLA will increase the number of output decode lines which are typically interconnected or routed to other circuits located in different parts of the same integrated circuit. As a result, there is necessitated a relatively large amount of physical space required for fabricating the interconnections thereby increasing the cost of the overall integrated circuit. Thus, it would be expedient to reduce the number of decode lines so as to minimize routing and the amount of required chip area.
In general, a PLA is a logic circuit which receives a plurality of digital input signals and generates a plurality of digital output signals wherein each of the digital output signals is a programmable sum-of-product combination of the input signals. In conventional programmable logic arrays, there is provided a two "plane" structure consisting of two separate regions or groupings of logic gates with the outputs of one region being fed into the inputs of the other region. For example, a basic PLA structure is comprised of an AND plane for generating a plurality of product terms which are the logical AND of selected input signals and an OR plane for generating the output signals by selectively ORing the AND terms. Since the digital input signals to the PLA consist of the opcode words and their complements, which are to be decoded, the primary concern is in relationship to the structure of the AND plane in the PLA.
A block diagram of a prior art arrangement of the AND plane in the PLA is illustrated in FIG. 1 and has been labeled "Prior Art." Here, the AND plane is designated generally by reference numeral 2 which receives on respective input lines 3 and 4 the digital input signal x(7:0) and its complement x(7:0). The input signal x(7:0) is an 8-bit word which represents the control command or the opcode word to be decoded. The input signal x(7:0) is the complement of the control command, i.e., x(7)=not x(7), x(6)=not x(6), and so on. The AND plane also receives a precharge signal on line 5 and an evaluation signal on line 6. While the precharge signal and the evaluation signal are shown as two different signals, it should be noted that they could be the same signal since only one of the two signals (precharge and evaluation) is active at any given time. Thus, with a opcode word having a length of eight bits there are a maximum of 256 outputs available on the output lines 7. Each one of the outputs correspond to a "leg" in the AND plane 2.
In FIG. 2, there is shown a detailed schematic circuit diagram of two legs of the AND plane 2 in the PLA of FIG. 1 for decoding two opcode words and their associated command controlled action generation circuitry. The first leg OUT(1A) is comprised of programming transistors N1-N8, a precharge transistor P1, and an evaluation transistor El. The 8-bit input signal x(7:0) is received on lines 10-24, and the complement signal x(7:0) is received on lines 26-40. The precharge/evaluate signal (PRCH/EVAL) is applied to input line 42 which is connected to the gates of the transistors P1 and E1. The first leg OUT(1A) is used to decode, for example, a first control word x.sub.1 (7:0) expressed in binary as 00011010 or in hexadecimal as Hex 1A. The complement x.sub.1 (7:0) or x.sub.1 L(7:0) of the first control word expressed in binary will be 11100101.
In order to decode the first control word x.sub.1 (7:0)=00011010, the eight programming transistors N1-N8 have their respective drain and source electrodes connected between the first output leg OUT(1A) on output line 44 and a Dynamic Ground line 46. The gate electrodes of the transistors N1-N8 are connected to receive corresponding input literals x.sub.1 (7), x.sub.1 (6), x.sub.1 (5), x.sub.1 L(4), x.sub.1 L(3), x.sub.1 (2), x.sub.1 L(1), and x.sub.1 (0) on the respective lines 10, 12, 14, 32, 34, 20, 38 and 24. The precharge transistor is comprised of P-channel MOS transistor and has its source connected to an upper power supply voltage or potential VDD, its drain connected to the output line 44, and its gate connected to receive the signal PRCH/EVAL on the input line 42. The evaluation transistor E1 is comprised of an N-channel MOS transistor and has its drain connected to the Dynamic Ground line 46, its source connected to a lower power supply voltage or reference ground potential GND, and its gate connected to receive also the signal PRCH/EVAL.
During the precharge phase (the signal PRCH/EVAL is at a low logic level), the transistor P1 is turned on so as to charge the output line 44 to a high level and the transistor E1 is turned off. During the evaluation phase when the signal PRCH/EVAL is at a high logic level, the transistor P1 is turned off and the transistor E1 is turned on so as to connect the Dynamic Ground line 46 to the reference ground potential GND. As a result, the high level on the output line 44 may then be discharged through certain ones of the programming transistors whose gate electrode is connected to a high or "1" logic level. However, in this case it will be noted that none of the programming transistors N1-N8 in the first leg will be turned on when the first control word is equal to 00011010 since all of the input literals will be at a low or "0" logic level. Consequently, the output OUT(1A) on the line 42 will remain charged to a high level.
Similarly, the second leg OUT(1B) is comprised of programming transistors N11-N18, a precharge transistor P2 and the evaluation transistor E1. It will be noted that while a separate precharge transistor is used for each leg the evaluation transistor E1 is shared. The signal PRCH/EVAL on the line 42 is also connected to the gate of the precharge transistor P2. The second leg OUT(1B) is used to decode, for example, a second control word x.sub.2 (7:0) expressed in binary as 00011011 (Hex 1B), which is the next higher binary number than the first control word. The complement x.sub.2 (7:0) or x.sub.2 L(7:0) of the second control word expressed in binary will be 11100100.
In order to decode the second control word 00011011, the eight programming transistors N11-N18 have their respective drain and source electrodes connected between the second leg OUT(1B) on line 48 and the shared Dynamic Ground line 46. The gate electrodes of the transistors N11-N18 are connected to receive corresponding input literals x.sub.2 (7), x.sub.2 (6), x.sub.2 (5), x.sub.2 L(4), x.sub.2 L(3), x.sub.2 (2), x.sub.2 L(1), and x.sub.2 L(0) on the respective lines 10, 12, 14, 32, 34, 20, 38 and 40. The precharge transistor P2 is comprised of a P-channel MOS transistor and has its source connected to the upper power supply potential VDD, its drain connected to the output line 48, and its gate connected to receive the signal PRCH/EVAL on the input line 42.
During the precharge phase, the transistor P2 is turned on so as to charge the output line 48 to a high level and the transistor E1 is turned off. During the evaluation phase, the transistor P2 is turned off and the transistor E1 is turned on. The high level on the output line 48 will be discharged through certain ones of the programming transistors whose gate electrode is connected to a high or "1" logic level. Again, it can be seen that none of the programming transistors N11-N8 of the second leg will be turned on when the second control word x.sub.2 (7:0) is equal to 00011011 since all of the input literals will be at a low or "0" logic level.
For a fully decoded PLA receiving an 8-bit control word, all of the 256 outputs will be charged to a high level during the precharge phase. During the evaluation phase, only one of the 256 outputs will remain charged for a given control word (the output leg having the programming transistors whose gates receive the input literals all equal to the logic "0") and all of the other ones will be discharged.
The associated command controlled action generation circuitry 50 is operatively connected to the output lines 44 and 48 of the PLA for generating a corresponding action in relation to a particular control word at some later point in time. The generation circuit 50 includes a first buffer 52a, a first latch circuit 54a, and a first transmission gate circuit 56a which are associated with the first output leg OUT(1A). The generation circuit 50 also includes a second buffer 52b, a second latch circuit 54b, and a second transmission gate 54b which are associated with the second output leg OUT(1B). Each of the first and second buffers 52a and 52b is formed by an inverter INV1. Each of the first and second latch circuits 54a and 54b is comprised of a pass transistor 58 and inverters INV2 and INV3. Each of the first and second transmission gate circuits 56a and 56b is comprised of a transmission gate TG, an inverter INV4, and a pull-down transistor 60.
While the signal PRCH/EVAL on the line 42 remains at the high level, a first clock signal CLK1 goes high after some delay time so as to send the outputs of the first and second buffers 52a and 52b into the respective first and second latch circuits 54a and 54b. The first clock signal CLK1 will then go low and after some more delay time, the second clock signal CLK2 will go high. Dependent upon the control command decoded and stored in the latch circuit, the second clock signal CLK2 will be passed through the transmission gate circuits so as to generate the corresponding action ACTION(1A) or ACTION(1B) on respective terminals 62 and 64.
The present invention represents an improvement over the prior art illustrated in FIG. 2 of the drawings. In particular, the logic circuit arrangement of the instant invention achieves the same functionality of the AND plane of FIG. 2 with the use of a smaller number of transistor components. This is achieved in the present logic circuit arrangement by organizing the AND plane so as to decode only the first seven (7) bits of the 8-bit opcode. The least significant bit of the opcode word is decoded separately and outside of the AND plane by a LSB decoder circuit.